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200201A-01

The PXIe-7820R is a multifunction RIO with a Kintex 7 160T FPGA for applications like waveform generation and HIL testing.

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    Description

    The PXIe-7820R is a system element categorized under the PXI R Series, designed to meet a wide range of testing and simulation needs. This multifunction device, with part numbers 200201A-01, PXIe-7820R, and 783484-01, is equipped with a powerful Kintex 7 160T FPGA, making it an ideal choice for applications requiring high-speed data processing and complex algorithm implementations.

    It boasts a significant amount of digital I/O, with 128 DIO channels, allowing for flexible interfacing with a variety of digital devices. The minimum I/O pulse width capability is 6.25 ns, complemented by a minimum testing period of 5 ns, ensuring precise timing and control for high-speed applications. The device accepts an external clock input, facilitating synchronization with external systems.

    The PXIe-7820R is designed with a characteristic impedance of 50 Ω and features a maximum input leakage of ± 15 μA. It defaults to a tristate power-on state, known as Tristate 1, which helps in protecting the digital I/O from long-term over/under-voltage exposure.

    Supported by LabVIEW FPGA software, this device enables users to develop custom applications and algorithms directly on the FPGA, providing versatility for a wide range of applications. These include, but are not limited to, waveform generation, sensor simulation, hardware-in-the-loop (HIL) testing, and the development of custom communication protocols.

    Feature Specification
    Part Number 200201A-01, PXIe-7820R, 783484-01
    Category PXI R Series
    Model PXIe-7820
    Description System Element, IES, CCA, PXIe-7820R, Kintex-7 160T (FPGA Only), R Series Multifunction Rio
    FPGA Kintex 7 160T
    Digital I/O 128 DIO
    Minimum I/O Pulse Width 6.25 ns
    Minimum Testing Period 5 ns
    External Clock Direction Input Into device
    Maximum Input Leakage ± 15 μA
    Characteristic Impedance 50 Ω
    Power-On State Tristate 1 (tristate by default of 2 NI recommends limiting long-term over/under-voltage exposure to the Digital I/O)
    Software LabVIEW FPGA
    Applications Waveform generation, sensor simulation, HIL testing, custom communication protocols,

    Question 1: What FPGA does the PXIe-7820R use?
    Answer 1: Kintex 7 160T FPGA

    Question 2: How many DIO channels does the PXIe-7820R have?
    Answer 2: 128 DIO channels

    Question 3: What is the minimum I/O pulse width of the PXIe-7820R?
    Answer 3: 6.25 ns

    Question 4: What software supports the PXIe-7820R for custom applications?
    Answer 4: LabVIEW FPGA

    Question 5: What is the purpose of Tristate 1 in the PXIe-7820R?
    Answer 5: Protects DIO from over/under-voltage