Description
The PXIe-7820R is a state-of-the-art PXI Digital Reconfigurable I/O Module, part of the PXI R Series, designed to meet a variety of demanding applications. With part numbers 156336D-01L, 783484-01, this module is equipped with a powerful Kintex-7 160T FPGA, making it capable of handling complex processing tasks with ease.
This module features 128 DIO (Digital I/O), providing ample connectivity for various digital devices. It is specifically designed to support high-speed, peer-to-peer streaming, allowing for efficient data transfer between modules. The PXIe-7820R is compatible with LabVIEW FPGA, offering a versatile and user-friendly programming environment for developing custom applications.
Applications for the PXIe-7820R are diverse and include waveform generation, sensor simulation, hardware-in-the-loop (HIL) testing, custom communication protocols, and error range testing. Its digital I/O is capable of achieving a minimum pulse width of 6.25 ns, with a testing period minimum of 5 ns, ensuring high precision in timing-critical applications.
Moreover, the module supports an external clock direction input and has a maximum input leakage of ± 15 μA. Its characteristic impedance is 50 Ω, making it compatible with standard digital signal environments. Additionally, the power-on state is set to Tristate 1, with NI recommending limiting long-term exposure to over/under-voltage conditions to protect the digital I/O.
In conclusion, the PXIe-7820R is a versatile and powerful module designed for a wide range of applications requiring high-speed digital I/O, offering robust features for advanced testing and simulation tasks.
| Specification | Detail |
|---|---|
| Part Number | 156336D-01L, 783484-01 |
| Category | PXI R Series |
| Model | PXIe-7820R |
| FPGA | Kintex-7 160T |
| Type | PXI Digital Reconfigurable I/O Module |
| Digital I/O | 128 DIO |
| Software | LabVIEW FPGA |
| Peer-to-Peer Streaming | Supported |
| Applications | Waveform generation, sensor simulation, HIL testing, custom communication protocols, error range testing |
| I/O Pulse Width | Minimum 6.25 ns |
| Testing Period | Minimum 5 ns |
| External Clock Direction Input | Supported |
| Maximum Input Leakage | ± 15 μA |
| Characteristic Impedance | 50 Ω |
| Power-On State | Tristate 1 (default of 2 NI recommends limiting long-term over/under-voltage exposure to the Digital I/O) |
